Traditional cell-based application specific integrated circuit (ASIC) layout designs typically include a set of regular cells that are interconnected to perform the desired function or logic of the ASIC. In particular, ASIC layout designs are common in very large scale integration (VLSI) of complex integrated circuits such as processors. In addition to the base set of functional logic cells, the ASIC layout designs typically comprise a plurality of spare cells that are randomly dispersed throughout the regular cells. The spare cells are included in the ASIC design for the purpose of correcting, altering or changing the functionality of the ASIC during an engineering change order (ECO) process.
There is a demand in the industry to increase the density of regular cells. There is also a demand to increase the density of interspersed spare cells to improve interconnectivity and functionality choices. However, with the ever increasing density of cells, has come an even more dramatic increase in overall power consumption. Typically, each cell, whether a regular cell or spare cell, contributes to the overall power consumption of the ASIC. It is therefore desirable to reduce the power consumption of the ASIC, and in particular the spare cells, in order to improve the overall efficiency of an integrated circuit.